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AD9850

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CMOS, 125 MHz

Complete DDS Synthesizer

FEATURES
125 MHz Clock Rate
On-Chip High Performance DAC and High Speed
Comparator
DAC SFDR > 50 dB @ 40 MHz AOUT
32-Bit Frequency Tuning Word
Simplified Control Interface: Parallel Byte or Serial
Loading Format
Phase Modulation Capability
3.3 V or 5 V Single-Supply Operation
Low Power: 380 mW @ 125 MHz (5 V)
Low Power: 155 mW @ 110 MHz (3.3 V)
Power-Down Function
Ultrasmall 28-Lead SSOP Packaging
APPLICATIONS
Frequency/Phase—Agile Sine Wave Synthesis
Clock Recovery and Locking Circuitry for Digital
Communications
Digitally Controlled ADC Encode Generator
Agile Local Oscillator Applications
GENERAL DESCRIPTION
The AD9850 is a highly integrated device that uses advanced
DDS technology coupled with an internal high speed, high
performance D/A converter and comparator to form a complete,
digitally programmable frequency synthesizer and
clock generator function. When referenced to an accurate
clock source, the AD9850 generates a spectrally pure, frequency/
phase programmable, analog output sine wave. This
sine wave can be used directly as a frequency source, or it can
be converted to a square wave for agile-clock generator applications.
The AD9850’s innovative high speed DDS core provides
a 32-bit frequency tuning word, which results in an output
tuning resolution of 0.0291 Hz for a 125 MHz reference clock
input. The AD9850’s circuit architecture allows the generation
of output frequencies of up to one-half the reference clock
frequency (or 62.5 MHz), and the output frequency can be digitally
changed (asynchronously) at a rate of up to 23 million new
frequencies per second. The device also provides five bits of
digitally controlled phase modulation, which enables phase
shifting of its output in increments of 180°, 90°, 45°, 22.5°,
11.25°, and any combination thereof. The AD9850 also contains
a high speed comparator that can be configured to accept the
(externally) filtered output of the DAC to generate a low jitter
square wave output. This facilitates the device’s use as an
agile clock generator function.
The frequency tuning, control, and phase modulation words are
loaded into the AD9850 via a parallel byte or serial loading
format. The parallel load format consists of five iterative loads
of an 8-bit control word (byte). The first byte controls phase
modulation, power-down enable, and loading format; Bytes 2 to
5 comprise the 32-bit frequency tuning word. Serial loading is
accomplished via a 40-bit serial data stream on a single pin. The
AD9850 Complete DDS uses advanced CMOS technology to
provide this breakthrough level of functionality and performance
on just 155 mW of power dissipation (3.3 V supply).
The AD9850 is available in a space-saving 28-lead SSOP,
surface-mount package. It is specified to operate over the
extended industrial temperature range of –40°C to +85°C.
Parameter Temp Test Level Min Typ Max Unit
CLOCK INPUT CHARACTERISTICS
Frequency Range
5 V Supply Full IV 1 125 MHz
3.3 V Supply Full IV 1 110 MHz
Pulse Width High/Low
5 V Supply 25°C IV 3.2 ns
3.3 V Supply 25°C IV 4.1 ns
DAC OUTPUT CHARACTERISTICS
Full-Scale Output Current
RSET = 3.9 kΩ 25°C V 10.24 mA
RSET = 1.95 kΩ 25°C V 20.48 mA
Gain Error 25°C I –10 +10 % FS
Gain Temperature Coefficient Full V 150 ppm/°C
Output Offset 25°C I 10 μA
Output Offset Temperature Coefficient Full V 50 nA/°C
Differential Nonlinearity 25°C I 0.5 0.75 LSB
Integral Nonlinearity 25°C I 0.5 1 LSB
Output Slew Rate (50 Ω, 2 pF Load) 25°C V 400 V/μs
Output Impedance 25°C IV 50 120 kΩ
Output Capacitance 25°C IV 8 pF
Voltage Compliance 25°C I 1.5 V
Spurious-Free Dynamic Range (SFDR)
Wideband (Nyquist Bandwidth)
1 MHz Analog Out 25°C IV 63 72 dBc
20 MHz Analog Out 25°C IV 50 58 dBc
40 MHz Analog Out 25°C IV 46 54 dBc
Narrowband
40.13579 MHz ± 50 kHz 25°C IV 80 dBc
40.13579 MHz ± 200 kHz 25°C IV 77 dBc
4.513579 MHz ± 50 kHz/20.5 MHz CLK 25°C IV 84 dBc
4.513579 MHz ± 200 kHz/20.5 MHz CLK 25°C IV 84 dBc
COMPARATOR INPUT CHARACTERISTICS
Input Capacitance 25°C V 3 pF
Input Resistance 25°C IV 500 kΩ
Input Current 25°C I –12 +12 μA
Input Voltage Range 25°C IV 0 VDD V
Comparator Offset* Full VI 30 30 mV
COMPARATOR OUTPUT CHARACTERISTICS
Logic 1 Voltage 5 V Supply Full VI 4.8 V
Logic 1 Voltage 3.3 V Supply Full VI 3.1 V
Logic 0 Voltage Full VI 0.4 V
Propagation Delay, 5 V Supply (15 pF Load) 25°C V 5.5 ns
Propagation Delay, 3.3 V Supply (15 pF Load) 25°C V 7 ns
Rise/Fall Time, 5 V Supply (15 pF Load) 25°C V 3 ns
Rise/Fall Time, 3.3 V Supply (15 pF Load) 25°C V 3.5 ns
Output Jitter (p-p) 25°C V 80 ps
CLOCK OUTPUT CHARACTERISTICS
Clock Output Duty Cycle (Clk Gen. Config.) 25°C IV 50 ± 10 %

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